1. Field of the Invention
The present invention pertains to a semiconductor manufacturing process. In particular, the present invention pertains to an integrated post-etch treatment method which is performed after etching of a dielectric surface, for the purpose of removing photoresist, byproducts remaining on the dielectric surface after the etch process, and for removing an anti-reflection (ARC) layer underlying the dielectric layer.
2. Brief Description of the Background Art
Since the development of the first integrated circuit device, the technology of semiconductor fabrication has focused on minimizing the feature size of semiconductor devices. With the advancements made in processing technologies such as deposition, lithography, etching, and thermal treatment, the packing density of integrated circuit chips has greatly increased. A single chip manufactured using the present semiconductor fabrication technology may include millions or even billions of devices such as transistors and capacitors. Therefore, the feature size of integrated circuit devices has been scaled down to a submicron level in order to attain the high packing density of fabricated chips.
On a single integrated circuit chip, various devices are connected through conductive interconnections. Generally, several layers of conductive structures with horizontal and vertical wirings are applied to a substrate to form the designed circuit connections. The conductive layers are insulated from each other using dielectric materials. A wiring layer of interconnections is typically composed primarily of a dielectric layer with the defined horizontal wiring members and downward-extended, vertical wiring members, often referred to as xe2x80x9cplugsxe2x80x9d.
Using the present metallization technology for forming interconnections, a dielectric layer is first formed on a substrate, then defined with openings in order to provides spaces for depositing conductive materials, which will connect with the underlying substrate. The conductive materials are deposited into openings, typically referred to as xe2x80x9ccontact viasxe2x80x9d, to form the vertical wirings. After a wiring pattern has been defined on the conductive layer, the horizontal wirings can be formed by depositing another conductive layer. When dual damascene technology is used, the horizontal wirings can be defined within the dielectric layer, such that the vertical and horizontal wirings can be formed simultaneously when the conductive materials are deposited into the vertical contact vias and horizontal channels which were previously defined in the dielectric layer.
Referring to FIG. 1, which shows a typical structure of the kind known in the art, an interconnection layer 12 is formed on a semiconductor substrate 10, and an anti-reflection layer (ARC) 14 is formed on the interconnection layer 12 for the purpose of improving the pattern-defining accuracy and resolution. The ARC layer 14 typically comprises a material such as titanium nitride. A dielectric layer 16 overlies the interconnection layer 12 and the ARC layer 14. To define the necessary openings for making vertical connecting plugs, a photoresist layer 18 is formed over the dielectric layer 16, with the designed pattern exposed and developed. The dielectric layer 16 is then etched using the photoresist layer 18 as a mask in order to define interlayer contact vias 20, as shown in FIG. 2. Generally, some residues may remain and some byproducts may be created during the etch process, such as the polymer 22 formed on the sidewall of the contact vias 20, as well as on the surrounding walls of the processing chamber. With the presence of the underlying interconnection layer 12 and ARC layer 14 in some of the etched regions, the deposited polymer 22 may contain metallic ions or molecules.
After the main etch step for defining the contact vias is completed, a series of processes are carried out to remove the remaining photoresist 18 and deposited residues and/or byproducts 22. This series of processes or process steps is frequently referred to as contact via definition finishing. The ARC layer 14 underlying the base of the contact via 20 is also typically removed in order to improve contact conductivity. In the conventional fabrication process, the etch process for finishing contact via definition typically includes three post-etch treatment steps, as shown in FIG. 4. After the main etch 30 is performed, a first phase post-etch treatment (PET) 32 is performed comprising a single step or a sequence of sub-steps to remove the photoresist 18 and residues or byproducts such as the deposited polymer 22. Then, a second etch step for removal of residual ARC layer 14 is carried out. Finally, in order to stabilize chamber conditions, a second phase post-etch treatment 36 is performed to clean the residue remaining on the substrate 10 and the processing chamber walls after the ARC layer etch step 34.
An earlier approach for post-etch treatment is described in copending U.S. application Ser. No. 09/183,778, filed Oct. 30, 1998, and titled: xe2x80x9cMethod Of Reducing Stop Layer Loss In A Photoresist Stripping Process Using Hydrogen As a Fluorine Scavengerxe2x80x9d. The application Ser. No. 09/183,778 is assigned to the assignee of the present invention and is hereby incorporated by reference in its entirety. In the earlier approach, the first phase post-etch treatment 32 typically includes three steps which comprise exposing the substrate to a high-flow oxygen plasma, followed by a low-flow oxygen plasma, followed by a cleaning step. However, this method has some disadvantages. For example, in the first phase of the post-etch treatment, the oxygen plasma has been found to be ineffective and inefficient at removing the deposited polymer 22, particularly the metal-comprising polymer generated during the main etch step 30. The presence of such residual metal-comprising polymer in the contact vias damages the contact between subsequently deposited conductive materials and the underlying interconnection layer 12. The accumulation of metal comprising polymer potentially interferes with the maintenance of a stable and predictable process chamber condition. The controllability of the process is reduced under unstable chamber conditions, resulting in degraded process windows and product yields. Furthermore, the traditional oxygen plasma treatment attacks the sidewalls of dielectric layer 16, altering the shape of the contact via 20.
During the anti-reflection etch 34 to remove the anti-reflection layer 14 (such as titanium nitride), the selectivity of etching the anti-reflection layer 14 relative to the dielectric layer 16 and the underlying aluminum interconnection material 12 may be poor, resulting in severe dielectric loss and/or aluminum sputtering. FIG. 3 illustrates the kind of sputtering of an underlying aluminum interconnection layer 12 which frequently occurs during the anti-reflection etch step 34. The multi-step post-etch process following the main etch 30 also increases the processing time and significantly reduces the wafer throughput of the contact via etch process.
The present invention pertains to an integrated post-etch treatment method which is performed after a dielectric etch process for the purpose of removing residual photoresist and byproducts remaining after the etch process. Through the process and chemistry of the present invention, the contact vias formed by etching a dielectric layer can be provided with an improved sidewall profile, and the process chamber conditions can be easily maintained, with less undesired residues and reduced polymer byproduct build-up both on contact via sidewalls and process chamber surfaces. The integrated post-etch treatment method of the present invention further removes an anti-reflection layer overlying an interconnection layer using fewer process steps than are used in conventional approaches.
According to the present invention, after the etch of dielectric material to define a pattern or spaces for filling, such as contact vias or interconnection channels, at least one post-etch treatment step is performed to remove residues remaining on the etched semiconductor structure surface. When an oxygen-containing and/or metal-containing ARC layer is present, this post-etch treatment step may also be used to remove an underlying ARC layer in applications such as the formation of interconnection layer plugs. Preferably, this treatment is performed in the same processing chamber as the dielectric etch. Preferably, the post-etch treatment step removes residual photoresist, while the residues and polymer deposits on the walls of the contact via are removed.
According to the method of the present invention, following the dielectric etch process, the semiconductor structure is exposed to a post-etch treatment step in which the structure is contacted with a plasma generated from a source gas comprising oxygen, a nitrogen-comprising gas, and a reactive gas comprising hydrogen, carbon, and fluorine. With the addition of the nitrogen-comprising gas and the reactive gas to an oxygen-containing plasma source gas, the etchant species generated effectively remove residues and polymers remaining in contact vias after dielectric etch.
The reactive gas preferably comprises at least one hydrogen-containing fluorocarbon gas, which is preferably selected from the group consisting of CHF3, CH2F2, CH3F, C3H2F6, and combinations thereof. Alternatively, the reactive gas comprises at least one fluorocarbon gas and hydrogen. The fluorocarbon gas is preferably selected from the group consisting of C2F6, C3F6, C3F8, C4F6, C4F8, and combinations thereof.
The nitrogen-comprising gas is preferably N2. The addition of nitrogen improves the dissociation of oxygen and other gas species and also enhances residue removal.
Using the method of the invention, the exposed portion of an oxygen-containing and/or metal-containing ARC layer overlying the interconnection layer may be removed, for the purpose of improving the conductivity of the interconnection layer. Using the method of the invention, the residual sidewall polymer, and in particular any metal-comprising polymer remaining after the dielectric etch process, can be cleanly removed.
An especially preferred embodiment method of the invention includes two additional steps: a flushing step, performed prior to the post-etch treatment step previously described, and a cleaning step, performed following the post-etch treatment step. The flushing step employs a high-flow oxygen-based plasma for the purpose of flushing out fluorine species which may remain in the chamber after the dielectric etch process. The cleaning step employs a medium-flow oxygen-based plasma which cleans the process chamber and provides a stabilized chamber condition free of undesired residual gases for subsequent processes. This latter cleaning step may alternatively be performed after removal of the semiconductor substrate from the process chamber.